feat(packages): add Europractice quad packages to PACKAGE_DEFINITIONS#170
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Expand PACKAGE_DEFINITIONS from 4 to 21 entries covering quad EP packages: PGA84/100s/100l/120/208, QFP64/120/160/208, QFN32-100. qfn16/qfn24 are below QuadPackageDef's 8-pins/side minimum (the bringup power-pin allocator needs height // 2 > 3); pga256/cc/dil/soic are documented as TODO in the backend's ep_packages.json. EP-specific cell names, layer conventions and pin_map strings live in chipflow-backend's packaging_klayout plugin so this library stays vendor-agnostic.
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Summary
Expand
PACKAGE_DEFINITIONSfrom 4 to 21 entries covering all quad EP packages (PGA84/100s/100l/120/144/208, QFP64/120/160/208, QFN32/40/48/56/64/80/88/100).chipflow-libstays vendor-agnostic — EP-specific cell names, layer conventions and pin-map strings live in chipflow-backend'spackaging_klayoutplugin (data/ep_packages.json).Notes
qfn16/qfn24are belowQuadPackageDef's 8-pins/side minimum (the bringup power-pin allocator needsheight // 2 > 3) and are intentionally absent. Their EP descriptors remain in the backend'sep_packages.jsonfor documentation.pga256(staggered double-row), CLCC and DIL/SOIC families are documented as v2 TODOs in the backend's_todo_v2_.Paired backend PR
Test plan
from chipflow.packages import PACKAGE_DEFINITIONS— all 21 entries instantiate (Pydantic validates).chipflow pin lockworks for designs that target any of the new packages.